This invention relates to a thin film transistor used in a static random access memory (SRAM), and more particularly to a thin film transistor and related fabrication method, which are suitable for large scale integration.
Thin film transistors have been used as load resistors in one megabyte (1M) SRAM memory cells, and as switching elements for operating pixels in an LCD.
To insure proper operation of the SRAM cell, the on/off current ratio of the thin film transistor should be increased. Preferably, this is achieved by increasing turn on current while decreasing turn off current. Thus, power consumption of the SRAM element can be reduced and memory characteristics of the SRAM element can be improved.
Recently, methods for fabricating transistors having improved on/off current ratios have been proposed. One such method will now be explained with reference to FIGS. 1a-1d.
FIG. 1a illustrates a first step in a process for fabricating an offset type thin film transistor. As seen in FIG. 1a, a gate 2 is formed by depositing a polysilicon film on an insulation substrate 1. The gate is then patterned with a photoetching process.
A gate insulation film 3 is then deposited on insulative substrate 1, and gate 2 is formed thereon. Gate 2 is formed by a chemical vapor deposition (CVD) process. In addition, a layer of polysilicon 4 is provided on gate insulation film 3. Ions are then implanted into polysilicon layer 4 for threshold voltage adjustment.
As shown in FIG. 1b, a photosensitive pattern 5 is formed on a portion of polysilicon film 4, while other portions, corresponding to a subsequently formed offset LDD (Lightly Doped Drain) region, remain exposed. The offset of the LDD region 6 is then formed in the body polysilicon film 4 at one side of the gate 2 by implanting impurity ions into the exposed polysilicon film 4, using photosensitive pattern 5 as an implantation mask. As shown in FIG. 1c, the photosensitive pattern 5 is removed, and another photosensitive pattern 7 is provided on polysilicon film 4 for forming source/drain regions 8.
Source/drain regions 8 are formed in polysilicon film 4 by implanting impurity ions having the same conductivity type as LDD region 6 into the polysilicon or polysilicon body film 4. In this step, photosensitive pattern 7 serves as an implantation mask. As shown in FIG. 1d, photosensitive pattern 7 is removed, resulting in a conventional thin film transistor having an offset structure.
In the conventional thin film transistor shown in FIG. 1d, a long channel length is required for assuring satisfactory element characteristics. On the other hand, large scale integration of the SRAM cell continues to advance, resulting in smaller device structures requiring that the channel length be reduced.
As the transistor size is scaled down and the channel length is reduced, however, transistor characteristics degrade significantly. Thus, transistor size has been a limiting factor in achieving large scale integration in SRAM chips. Further, the photoetching process defining the length of the offset region, causes a serious length change, which results in poor memory cell characteristics.
FIGS. 2a-2d illustrate an alternative conventional method for fabricating a thin film transistor.
Referring to FIG. 2a, a gate 11 is first formed on an insulation substrate 10. A gate insulation film 12 is then formed on the entire substrate surface, and a polysilicon body in the form of a film 13 is respectively formed thereon. After forming polysilicon body 13, impurity ions are implanted into polysilicon body 13 for threshold voltage adjustments.
As shown in FIG. 2b, LDD regions 15 are next formed in the polysilicon body 13 on opposite sides of the gate 11 by providing a photosensitive pattern 14 on the polysilicon body 13, and implanting impurity ions into polysilicon body 13 using photosensitive pattern 14 as an implantation mask.
Referring to FIG. 2c, spaces 16 are formed on opposite sides of the photosensitive pattern 14 by forming first an oxide film on the entire substrate surface and then etching back the oxide film in an appropriate manner. High density source/drain regions 17 are formed in the polysilicon body 13 by implanting impurity ions having the same conductivity type as the LDD regions 15 in polysilicon film 13. Photosensitive pattern 14 and spacers 16 are used as implantation masks in this step.
As shown in FIG. 2d, a conventional thin film transistor having an LDD structure is thus obtained by removing oxide film spacers 16 and photosensitive pattern 14.
The conventional LDD thin film transistor shown in FIG. 2d is advantageous in that it can eliminate the photoetching step used to fabricate the offset type thin film transistor shown in FIGS. 1a to 1d. However, the process for fabricating the LDD thin film transistor includes the steps of oxide film fabrication, oxide film spacer process, and removal processes. Fabrication of the LDD thin film transistor is therefore complication. Further, the size of the oxide film spacers suffers from poor reproducibility.